APA (7th ed.) Citation

Vaidyanathan, K. Design Technology Co-Optimization in the Era of Sub-Resolution IC Scaling. SPIE Digital Library.

Chicago Style (17th ed.) Citation

Vaidyanathan, Kaushik. Design Technology Co-Optimization in the Era of Sub-Resolution IC Scaling. SPIE Digital Library.

MLA (8th ed.) Citation

Vaidyanathan, Kaushik. Design Technology Co-Optimization in the Era of Sub-Resolution IC Scaling. SPIE Digital Library.

Warning: These citations may not always be 100% accurate.