Mixed FBB and RBB low leakage technique for high durable CMOS circuit
This conference paper was presented in the 2014 International Conference on Informatics, Electronics and Vision, ICIEV 2014; Dhaka; Bangladesh; 23 May 2014 through 24 May 2014 [© 2014 IEEE Computer Society] The conference paper's definite version is available at: http://10.1109/ICIEV.2014.6850...
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© 2014 IEEE Computer Society
2016
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| Rochtain ar líne: | http://hdl.handle.net/10361/7035 |
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10361-70352016-11-29T09:02:26Z Mixed FBB and RBB low leakage technique for high durable CMOS circuit Barua, Parag Jafar, Imran Bin Sengupta, Prianka Noor, Md Sadaf Department of Electrical and Electronic Engineering BB-Back Bias CMOS Circuits FBB-Forward Back Bias Gate leakage Leakage current Low leakage Low Power VLSI RBBReverse Back Bias Tunneling current This conference paper was presented in the 2014 International Conference on Informatics, Electronics and Vision, ICIEV 2014; Dhaka; Bangladesh; 23 May 2014 through 24 May 2014 [© 2014 IEEE Computer Society] The conference paper's definite version is available at: http://10.1109/ICIEV.2014.6850716 CMOS logic circuit is extensively used for designing low power Very Large Scale Integration (VLSI). Reducing the dimension of CMOS in a nanometer range, functionality and efficiency can be increased, but as a result we have to compromise with circuit level leakage. As circuit level leakage also known as leakage current is currently one of the major concernments to the VLSI designers. These Leakage currents are generated due to different types of leakage current components such as Weak inversion current, Drain-induced barrier lowering (DIBL), Gate-induced drain leakage and Oxide leakage tunneling. However, there are wide ranges of method that are already available to reduce these leakages, but all of them have their own tradeoffs. In this paper we propose a novel technique by integrating the idea of Forward Back Bias (FBB) and Reverse Back Bias (RBB) which reduces leakage extensively than sleepy stack, stacked sleep, variable body biasing and dual sleep. Furthermore, RBB and FBB are yielded with forced stacked transistors where RBB is accountable for nullifying the leakage and FBB is responsible for offsetting the delay penalty. The proposed method is scrutinized under 22nm to 65nm feature size, and it has come out that these novel schemes are especially very effective for designing the future low-voltage, low-power CMOS VLSI's [1]. Therefore, the main principle of this technique is to trim down leakages, but it has an obvious delay constraint that is considered as a tradeoff in this particular case. Published 2016-11-29T09:00:43Z 2016-11-29T09:00:43Z 2014 Conference Paper Barua, P., Jafar, I. B., Sengupta, P., & Noor, M. S. (2014). Mixed FBB and RBB low leakage technique for high durable CMOS circuit. Paper presented at the 2014 International Conference on Informatics, Electronics and Vision, ICIEV 2014, doi:10.1109/ICIEV.2014.6850716 978-147995179-6 http://hdl.handle.net/10361/7035 10.1109/ICIEV.2014.6850716 en http://ieeexplore.ieee.org/document/6850716/ © 2014 IEEE Computer Society |
| institution |
Brac University |
| collection |
Institutional Repository |
| language |
English |
| topic |
BB-Back Bias CMOS Circuits FBB-Forward Back Bias Gate leakage Leakage current Low leakage Low Power VLSI RBBReverse Back Bias Tunneling current |
| spellingShingle |
BB-Back Bias CMOS Circuits FBB-Forward Back Bias Gate leakage Leakage current Low leakage Low Power VLSI RBBReverse Back Bias Tunneling current Barua, Parag Jafar, Imran Bin Sengupta, Prianka Noor, Md Sadaf Mixed FBB and RBB low leakage technique for high durable CMOS circuit |
| description |
This conference paper was presented in the 2014 International Conference on Informatics, Electronics and Vision, ICIEV 2014; Dhaka; Bangladesh; 23 May 2014 through 24 May 2014 [© 2014 IEEE Computer Society] The conference paper's definite version is available at: http://10.1109/ICIEV.2014.6850716 |
| author2 |
Department of Electrical and Electronic Engineering |
| author_facet |
Department of Electrical and Electronic Engineering Barua, Parag Jafar, Imran Bin Sengupta, Prianka Noor, Md Sadaf |
| format |
Conference Paper |
| author |
Barua, Parag Jafar, Imran Bin Sengupta, Prianka Noor, Md Sadaf |
| author_sort |
Barua, Parag |
| title |
Mixed FBB and RBB low leakage technique for high durable CMOS circuit |
| title_short |
Mixed FBB and RBB low leakage technique for high durable CMOS circuit |
| title_full |
Mixed FBB and RBB low leakage technique for high durable CMOS circuit |
| title_fullStr |
Mixed FBB and RBB low leakage technique for high durable CMOS circuit |
| title_full_unstemmed |
Mixed FBB and RBB low leakage technique for high durable CMOS circuit |
| title_sort |
mixed fbb and rbb low leakage technique for high durable cmos circuit |
| publisher |
© 2014 IEEE Computer Society |
| publishDate |
2016 |
| url |
http://hdl.handle.net/10361/7035 |
| work_keys_str_mv |
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