Novel approaches to low leakage and area efficient VLSI Design

his thesis report is submitted in partial fulfillment of the requirements for the degree of Bachelor of Science in Electrical and Electronic Engineering, 2011.

Détails bibliographiques
Auteurs principaux:	Izma, Tajrian, Barua, Parag, Rahman, Md. Rejaur, Sengupta, Prianka
Autres auteurs:	Islam, Md. Shafiqul
Format:	Thèse
Langue:	English
Publié:	BRAC University 2011
Sujets:	Electrical and electronic engineering
Accès en ligne:	http://hdl.handle.net/10361/1469

id	10361-1469
record_format	dspace
spelling	10361-14692019-09-29T05:43:21Z Novel approaches to low leakage and area efficient VLSI Design Izma, Tajrian Barua, Parag Rahman, Md. Rejaur Sengupta, Prianka Islam, Md. Shafiqul Department of Electrical and Electronic Engineering, BRAC University Electrical and electronic engineering his thesis report is submitted in partial fulfillment of the requirements for the degree of Bachelor of Science in Electrical and Electronic Engineering, 2011. Cataloged from PDF version of thesis report. Includes bibliographical references (page 51-53). The development of digital integrated circuits is challenged by higher power consumption. The combination of higher clock speeds, greater functional integration, and smaller process geometries has contributed to significant growth in power density. Scaling improves transistor density and functionality on a chip. Scaling helps to increase speed and frequency of operation and hence higher performance. As voltages scale downward with the geometries threshold voltages must also decrease to gain the performance advantages of the new technology but leakage current increases exponentially. Thinner gate oxides have led to an increase in gate leakage current. Today leakage power has become an increasingly important issue in processor hardware and software design. With the main component of leakage, the sub-threshold current, exponentially increasing with decreasing device dimensions, leakage commands an ever increasing share in the processor power consumption. In 65 nm and below technologies, leakage accounts for 30-40% of processor power. According to the International Technology Roadmap for Semiconductors (ITRS) [1], leakage power dissipation may eventually dominate total power consumption as technology feature sizes shrink. While there are several process technology and circuit-level solutions to reduce leakage in processors, we propose novel approaches for reducing both leakage and dynamic power with minimum possible area and delay trade off. Tajrian Izma Parag Barua Md. Rejaur Rahman Prianka Sengupta B. Electrical and Electronic Engineering 2011-11-15T07:04:43Z 2011-11-15T07:04:43Z 2011 2011-08 Thesis ID 09221088 ID 09221082 ID 09221157 ID 09221092 http://hdl.handle.net/10361/1469 en BRAC University thesis are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. 65 pages application/pdf BRAC University
institution	Brac University
collection	Institutional Repository
language	English
topic	Electrical and electronic engineering
spellingShingle	Electrical and electronic engineering Izma, Tajrian Barua, Parag Rahman, Md. Rejaur Sengupta, Prianka Novel approaches to low leakage and area efficient VLSI Design
description	his thesis report is submitted in partial fulfillment of the requirements for the degree of Bachelor of Science in Electrical and Electronic Engineering, 2011.
author2	Islam, Md. Shafiqul
author_facet	Islam, Md. Shafiqul Izma, Tajrian Barua, Parag Rahman, Md. Rejaur Sengupta, Prianka
format	Thesis
author	Izma, Tajrian Barua, Parag Rahman, Md. Rejaur Sengupta, Prianka
author_sort	Izma, Tajrian
title	Novel approaches to low leakage and area efficient VLSI Design
title_short	Novel approaches to low leakage and area efficient VLSI Design
title_full	Novel approaches to low leakage and area efficient VLSI Design
title_fullStr	Novel approaches to low leakage and area efficient VLSI Design
title_full_unstemmed	Novel approaches to low leakage and area efficient VLSI Design
title_sort	novel approaches to low leakage and area efficient vlsi design
publisher	BRAC University
publishDate	2011
url	http://hdl.handle.net/10361/1469
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Novel approaches to low leakage and area efficient VLSI Design

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